[gclist] precise access barrier with hardware dirty bits
Thu, 8 Jul 1999 19:21:34 +0200
I had an idea last night that I wanted to share with you GC experts.
The idea was to use dirty bits of paging hardware to achieve _precise_
read or write barriers for a GC or persistent store,
by using one logical page mapping by logical object on a same (physical) page?
i.e. a same physical page P1 could contain three logical objects A, B, C,
at different offsets, and would accordingly be mapped three times
at different addresses logical virtual memory. Assuming your language
is strongly typed and your implementation is otherwise correct,
you could then track down _precisely_ at a _fine grained_
which of the objects on the page is being read or modified,
despite the hardware having only page-level granularity!
You could thus save some work for the GC,
at the expense of wasting address space
and increasing the cost of TLB management and misses
(which probably makes the trick useless on 32-bit architectures
and interesting only for 64-bit architectures).
And since you may map a physical page exactly as many times
as it has logical objects on it, you don't waste much physical resources
(the per-object GC meta-information is moved from concatenated headers
to the page table structure, which may also help in some cases,
like not mixing administrative pointers and data,
or not having a special case for page-aligned raw data buffers).
Has anyone considered the efficiency tradeoffs of such an approach?
Has anyone implemented it?
Is it completely worthless for some reason I don't understand,
or has it any value? Is it already well-known?
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