Samsung announces 0.35 micron ASIC family featuring 24Mb of embedded DRAM in a unified process
Samsung Semiconductor by way of firstname.lastname@example.org Henry Baker
Mon, 5 May 1997 6:49:14 PDT
Samsung announces 0.35 micron ASIC family featuring 24Mb of embedded
DRAM in a unified process; ASIC design centers support core-based
"system-on-a-chip" design methodology; ASIC family backed by Samsung's
high volume manufacturing
SAN JOSE, Calif.--(BUSINESS WIRE)--May 5, 1997--Samsung
Semiconductor, Inc. today announced the introduction of a new deep
submicron ASIC family based on its 0.35 micron process technology.
This new ASIC family is the industry's first to be simultaneously
available in cell-based (STD90), gate array (KG90), customer-owned
tooling (COT), and merged DRAM and logic (MDL90) options.
Samsung's cell-based ASICs offer more than 2 million gates of
random logic, while the MDL ASICs allow designers to embed up to 24
megabits (Mb) of single transistor EDO DRAM or SDRAM. This new 0.35
micron ASIC family also provides a wide offering of processor cores,
I/O and analog blocks, as well as a comprehensive library of digital
Samsung's diversity in consumer electronics, telecommunications
and semiconductors has provided the company's ASIC group with a
wealth of system-level knowledge and experience. This expertise
helped Samsung craft its "system-on-a-chip" design methodology and
identify the right combination of cores and macrocells its customers
would need. Samsung gives its ASIC customers a time to market
advantage by providing this "system-on-a-chip" design capability at
all of its ASIC design centers.
The company has established submicron ASIC manufacturing capacity
at four facilities and also plans to manufacture 0.35 micron and
below technologies at the Austin, Texas, plant. Samsung will continue
its ASIC roadmap with plans to reach a 0.25 micron geometry by 1998,
and 0.18 by 1999.
"Samsung has become the global market leader in several product
categories, such as DRAMs, SRAMs and CDMA handsets, and has similar
plans for the ASIC market," said Farzad Zarrinfar, Sr. Product
Marketing Manager for Samsung's ASIC Group. "The combination of
Samsung's merged DRAM and logic capability, industry standard cores,
library of function blocks, design center expertise and high volume
manufacturing allows us to provide the 'system-on-a-chip' designer
with the total solution necessary to move their high integration
designs into the next century."
Key markets for Samsung cell-based, COT and gate array ASICs
include networking, telecommunications and computers. The MDL ASIC
architecture is best suited for high integration applications, such
as 3D/2D graphics, wireless communications, set-top boxes, digital
video disk (DVD) systems, interactive video games, Ethernet/ATM
switches, graphics/MPEG frame buffers and on-chip cache for CPU
Samsung Perfects MDL Process Technology
Samsung is leading the merged DRAM and logic technology movement,
having developed a unified process for optimizing system-on-a-chip
performance. Samsung achieves optimized performance by using a
three-well merged DRAM and logic process. This allows Samsung's MDL
customers to gain an advantage with designs that provide superior
Other manufacturers offering ASICs with on-chip DRAM are using a
basic DRAM process rather than merged DRAM logic integration. Using
a DRAM process results in "system-on-a-chip" ASICs that experience
up to a 40 percent degradation in performance. This is because the
DRAM process has a higher threshold voltage (VT), which reduces
switching (speed) performance.
The MDL cell-based architecture allows the designer to bring
large memory blocks on-chip to achieve a true "system-on-a-chip"
implementation. This architecture provides several benefits,
including superior price per performance, higher speed and
reliability (because of fewer solder joints and packaging
interconnects) and a smaller form factor due to fewer components
occupying the printed circuit board.
Merged DRAM and logic also reduces power consumption and
minimizes the number of pins required for memory interface by 35 to
150 pins, depending upon configuration. As a result, cost-effective
plastic packages such as PQFP, TQFP, PLCC and PBGA, can be used.
With the high granularity of the memory banks, designers are able
to further reduce costs because they can select and use exactly the
amount and organization of memory required by their specific
Samsung's 0.35 micron MDL90 ASIC technology is already being used
in the design of Trident Microsystems' next-generation notebook
multimedia accelerator, where Trident is combining SDRAM, logic and
analog circuitry all on the same die.
"Samsung is one of the few ASIC companies that truly understands
the integration of mixed analog and digital circuitry," said Frank
Lin, president and CEO of Trident Microsystems, Inc. "Samsung's
merged DRAM and logic architecture and process technology has enabled
us to develop a notebook multimedia accelerator that will offer OEMs
significant power savings, a smaller footprint and vastly improved
Chips and Technologies has also selected Samsung's MDL90
technology for its new family of HiQVideo(TM) flat panel
video/graphic accelerators with embedded memory. "Samsung is a
leader in merged DRAM and logic ASIC technology," said Keith Angelo,
vice president of marketing at Chips and Technologies, Inc. "By
adding leading edge embedded memory to our HiQVideo family, we can
offer new highly integrated, low power, high performance products for
value line notebook designs."
Key Features of 0.35 Micron ASIC Family
The new Samsung ASIC family features a 0.35 micron channel length
for extremely high integration. The deep submicron design rules
allow for a 3.3 volt core for high performance and low power
consumption. All Samsung ASIC options are compatible with I/O
voltages ranging from 3.3 to 5.0 volt tolerant I/O.
Samsung's deep submicron ASIC architecture is based on 3- and
4-level metal with 3-level Poly/Ti Salicide on S&D. These new ASICs
achieve a high density of up to 18,000 raw gates per square
millimeter. The gate delay for a 2-input NAND device is
characterized to achieve 150 picoseconds (ps) at 3.3 volts, in a
Samsung's 0.35 ASIC technology offers compiled SRAM in
organizations such as 16K x 128 and 16K x 256. The MDL90 version is
capable of integrating single transistor DRAM memory organizations
such as 256K x 4, 128K x 64, 64K x 256 and 96K x 256.
Samsung provides an unsurpassed level of ASIC quality by
supporting a comprehensive test methodology that includes IEEE 1149.1
JTAG boundary scan, internal scan-based Automatic Test Pattern
Generation (ATPG), RAMBIST, fault grading, IDDQ and mixed-signal
I/O Library Support
Samsung offers a comprehensive portfolio of I/O buffers for its
sub-half micron technology. These include I/Os such as:
-- Accelerated graphics port (AGP)
-- Peripheral component interconnect (PCI)
-- ATA-3 ("mobile disk interface")
-- SCSI-3 (small computer systems interface)
-- Universal Serial Bus (USB)
-- Low voltage differential signaling (LVDS)
Spice models for high performance I/Os are also provided for
crosstalk analysis at the system level.
Core and Macrocell Support
Samsung's deliverables for embedded cores include items such as
Verilog/ VHDL models, Synopsys models, and wire-bonded test chips
(e.g. packaged ARM7TDMI core, Oak DSP Core and video encoder). A
software development toolkit featuring items such as assembler,
debugger, compiler, linker is available, as well. Samsung provides
the following cores and macrocells:
-- ARM7TDMI Core
-- A to D, D to A Converter
-- Oak DSP Core
-- 300MHz RAMDAC/PLL
-- 80C52 Microcontroller
-- video encoders/decoders
-- Z-80 processor core
In the future, Samsung plans to comply with VSI (Virtual Socket
Interface) compliant cores and design methodology.
Samsung's STD90, KG90 and MDL90 family of highly integrated ASICs
are available in a variety of different packaging options. These
include PQFP, TQFP, PLCC and PBGA packages, which are best suited for
high volume applications.
Design Tool Support
The new Samsung 0.35 micron ASIC family is supported by "open"
EDA design tools from industry leaders such as Avant!, Cadence,
Mentor, Synopsys and Viewlogic. Samsung customers can also enhance
their toolset with value-added Samsung tools, such as delay
prediction and automatic test program generation.
"Because Samsung allows sign-off with "open" design tools, the
customer does not have to learn the ASIC vendor's proprietary tools
-- that saves valuable time," added Zarrinfar. "Open design tools
and methodologies from the industry leaders, along with global access
to Samsung design centers and applications support, are critical for
the successful implementation of 'system-on-a-chip' designs."
Pricing and Availability
Pricing is dependent on design specifications, architecture,
complexity of design, package type and customer required services.
Non-recurring engineering (NRE) charges begin at $100,000. Contact
Samsung directly for business negotiation and pricing details.
Design kits for all Samsung 0.35 micron ASIC options will be
available in August 1997. The STD90, KG90 and MDL90 ASICs will
sample in September 1997, with production volumes beginning in Q4
1997. Samsung's COT option is available now.
Samsung used the Alpha 21164 processor, running at 500MHz, to
qualify its "now available" 0.35 micron process. In comparison,
some ASIC manufacturers use simple logic to qualify their process.
Samsung Semiconductor is a wholly owned subsidiary of Samsung
Electronics, an $18.8 billion dollar division of the $88 billion,
Korean-based, Samsung Group. Samsung's Semiconductor Division is the
seventh largest semiconductor manufacturer and the leading producer
of memory products in the world.
Samsung Semiconductor's North American headquarters are located
in San Jose. Samsung was the first company to introduce the
64-Megabit DRAM and the first fully functional 256-Megabit DRAM in
1994. In November 1996, Samsung developed the world's first
1-Gigabit DRAM. Samsung's non-memory products, called System LSI,
include ASICs, microcontrollers, power devices and the Alpha
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