I want to play with making hardware targeting a SLATE-based environment.

[Glenn Alexander]

On Thursday 27 March 2003 14:48, Brian T Rice <water at tunes.org> wrote:

> Interesting. Are you familiar with SqueakOS/SqueakNOS and such? There is
> also the Merlin project which gets into this kind of thing. See
> http://merlintec.com:8080/hardware for the hardware and
> http://merlintec.com:8080/software for the corresponding Self dialect
> idea.
>
I have been playing with Squeak for several months. I love it! But there are a few things about Smalltalk I dislike and Slate 
addressess all my issues.

I will check out Merlin. I am patient! ;-) Once Slate is bootstrapable outside of CVS I might even write some silly little code toys 
for it (the limits of my programing ability).

> > I am wondering what CPU characteristics would be important for a language
> > like SLATE. 
>
> We're attempting to make Slate adaptible to various architectures,
> actually, by avoiding a virtual machine tendency that standardize on
> intermediate-level encoding of operations. So this should not be too much
> of an issue.

That's the impression I got from my readings. But some arches handle these things better than others.

> I don't put too much stock in architecture types, although
> dynamic object environments tend to place a tax more on the memory
> architecture than the CPU pipelines.
>
Interesting. I am playing around with some ideas for a fairly radical memory architecture that would probably fit the bill here 
quite well.

> In general, I suppose that like most architectures, ones with a greater
> number of registers tend to be easier compiler and optimizer targets.

I have always been a bit shy of ARM's 16-register set. MIPS looks good with 32 regs. SH5 has 64 (Wheeee!) but I haven't had a good 
look into that architecture yet (downloaded the specs yesterday) and am not sure if anyone actually makes hard silicon here yet 
anyway.

> Perhaps someone else can comment more, as I usually focus on high-level
> design.

I don't expect anyone to be able to say 'this processor is best' as that would take extensive testing that would require a fairly 
finished software base, but knowing to steer clear of low-register-count architectures and to look hard at high memory-bandwidth 
solutions is probably enough to hint me in the right direction.

Might be a choice between an ARM/Alchemy MIPS device and a Transmeta Crusoe (although it is convoluted x86, I imagine the well-used 
parts of the Slate interpreter would end up well optimised in the VLIW code cache pretty quickly - I'll email Transmeta and ask).

If only the F-CPU project were further along. That arch makes me drool. Oh well. ;-)

--------------------------------------------------------
Glenn Alexander - The man with no surname and a silly hat.
(B.Teach, B.Ed Major IT Education, University of Wollongong Australia)
(Now available in China!)

http://www.shoalhaven.net.au/~glenalec
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