Genera

[P. T. Withington]

On 4/3/98 10:31, Chris Bitmead wrote:

>> Most importantly, it carries the 8-bits of tag through the entire datapath 
>and
>> memory interface.  The microengine can do tag comparison and dispatch in 
>parallel
>> with an operation, so for example an add instruction can assume that the 
>operands
>> are both fixnums and start doing the addition at the same time that the tag
>> comparison hardware is comparing the tags.  If there is a mismatch, that 
>microcycle
>> causes the result not to be stored and a trap to be taken.
>
>I heard the Sparc architecture has some support for tagged
>designs. Is it comparable in that respect or not?

The SPARC only supports 2-bit tags and does so by stealing from the 
32-bit word.  In tagged mode, you only get 30-bit integers.  The LispM 
supports 8-bit tags and full 32-bit integers.

>> The chip also has hardware support for ephemeral garbage collection, an 
>interface
>> to a co-processor, a way to do efficient burst mode transfers on the memory 
>bus,
>> and a special limited mode (FEP mode) for running some much more stylized 
>Lisp
>> code the load the virtual image, etc.
>
>How much of the GC is coded in hardware?

The hardware support for GC on the LispM consists of word-granularity 
read barriers, page-granularity remembered sets, and invisible forwarding 
pointers.  The collector itself is all software.

The Open Genera emulator uses techniques similar to:

Title:         Real-time Concurrent Collection on Stock Multiprocessors
Authors:       Andrew Appel; John R. Ellis; Kai Li
Publisher:     
Pub. Date:     07/88
Ident:         ACM PLDI 88, SIGPLAN Notices 23, 7 (July 88), pp. 11-20