Fri, 03 Apr 1998 15:31:39 +0000
> Most importantly, it carries the 8-bits of tag through the entire datapath and
> memory interface. The microengine can do tag comparison and dispatch in parallel
> with an operation, so for example an add instruction can assume that the operands
> are both fixnums and start doing the addition at the same time that the tag
> comparison hardware is comparing the tags. If there is a mismatch, that microcycle
> causes the result not to be stored and a trap to be taken.
I heard the Sparc architecture has some support for tagged
designs. Is it comparable in that respect or not?
> The chip also has hardware support for ephemeral garbage collection, an interface
> to a co-processor, a way to do efficient burst mode transfers on the memory bus,
> and a special limited mode (FEP mode) for running some much more stylized Lisp
> code the load the virtual image, etc.
How much of the GC is coded in hardware?