PowerPC CPU architecture Q

[Glenn Alexander]

Hi all, 
 
I am wondering what opinion is on PowerPC architecture performance for 
this (Slate) type of dynamic compilation. My own readings indicate 
that the PowerPC instruction set, while a lot better than x86, is 
still rather convoluted. How -in general - would PowerPC stack up 
against RISC CPUs with much simpler ISAs for dynamic compilation? I'm 
sure it is a lot more complex than just having a simple ISA! Just 
after general impressions, not benchmarked proofs. 
 
Regards, Glenn