PowerPC CPU architecture Q

[Lee Salzman]

Well, for dynamic compilation, the simplicity of the instruction set
isn't so much the big deal. It's just that if the instruction set has
some hard to use features, such as SIMD, then these things will tend not
to get used at all. They require analyses that are too expensive
to use in anything but static/explicit compilation. You can't use something
pervasively and implicitly if it needs analyses that cost far more than the 
cumulative running time of the optimized code!

You want code generation to be cheap, and a simpler processor ISA
perhaps means just the opposite. Take a look at just about any VLIW 
processor and especially the Itanium.

Aside from that, any architecture that is compiler-friendly in general
is very good. The PPC is rather compiler-friendly. Moreso than the x86,
but not terribly much more. Lots of registers - good. Fairly uniform
instruction set - good. Reasonable but not oversimplified addressing
modes - also really good. Some oddities in the instruction encoding.
Overall, though, still quite good.

Lee

On Tue, May 18, 2004 at 09:30:51AM +1000, Glenn Alexander wrote:
> Hi all, 
>  
> I am wondering what opinion is on PowerPC architecture performance for 
> this (Slate) type of dynamic compilation. My own readings indicate 
> that the PowerPC instruction set, while a lot better than x86, is 
> still rather convoluted. How -in general - would PowerPC stack up 
> against RISC CPUs with much simpler ISAs for dynamic compilation? I'm 
> sure it is a lot more complex than just having a simple ISA! Just 
> after general impressions, not benchmarked proofs. 
>  
> Regards, Glenn 
>